LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY speaker IS
PORT(clock:IN Std_logic;
speaker_out:OUT Std_Logic);
END speaker;
ARCHITECTURE behave OF speaker IS
SIGNAL state: std_logic_vector(1 downto 0);
BEGIN
PROCESS(clock)
BEGIN
IF rising_edge(clock) THEN
CASE state IS
WHEN "00" => state <= "01"; speaker_out <= '1';
WHEN "01" => state <= "10"; speaker_out <= '0';
WHEN "10" => state <= "11"; speaker_out <= '1';
WHEN "11" => state <= "00"; speaker_out <= '0';
WHEN OTHERS => state <= "00"; speaker_out <= '0';
END CASE;
END IF;
END PROCESS;
END behave;