library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity a is
port(clk:in std_logic;
data_in:in std_logic;
data_out:out std_logic_vector(7 downto 0));
end a;
architcture art of a is
signal temp:std_logic_vector(7 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
temp<=temp(7 downto 1)&datain;
end if;
end process;
end art;
我没有编译过 你看用的起不
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