求程序。VHDL 实现12位的二进制，转换BCD码

这个是十进制的

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT10 IS
PORT (CLK,RST: IN STD_LOGIC;
CQ: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COUT: OUT STD_LOGIC );
END CNT10 ;
ARCHITECTURE behav OF CNT10 IS
BEGIN
PROCESS(CLK,RST)
VARIABLE CQI:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF RST='1' THEN
CQI:=(OTHERS =>'0');
ELSIF CLK'EVENT AND CLK='1' THEN
IF CQI<9 THEN CQI:=CQI+1;
ELSE CQI:=(OTHERS=>'0');
END IF;
END IF;
IF CQI=9 THEN COUT<='1';
ELSE COUT<='0';
END IF;
CQ<=CQI;
END PROCESS;

看错了，理解错了
END behav;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity B_BCD is
port(clk:in std_logic;
din:in std_logic_vector(26 downto 0);
y0,y1,y2,y3,y4,y5,y6,y7:out std_logic_vector(3 downto 0));
end B_BCD;
architecture behav of B_BCD is
type state is (s0,s1,s2);
signal present_state:state;
signal mid_in:std_logic_vector(26 downto 0);
signal d0,d1,d2,d3,d4,d5,d6,d7:std_logic_vector(3 downto 0);
begin

process(clk)is
begin
if clk'event and clk='1' then
mid_in<=din;
present_state<=s0;

case (present_state) is
when s0=>
d0<="0000";d1<="0000";d2<="0000";d3<="0000";d4<="0000";d5<="0000";d6<="0000";d7<="0000";
present_state<=s1;
when s1=>
if mid_in>="100110001001011010000000" then mid_in<=mid_in-"100110001001011010000000";
d7<=d7+1;
present_state<=s1;
elsif mid_in>="000011110100001001000000" then mid_in<=mid_in-"000011110100001001000000";
d6<=d6+1;
present_state<=s1;
elsif mid_in>="000000011000011010100000" then mid_in<=mid_in-"000000011000011010100000";
d5<=d5+1;
present_state<=s1;
elsif mid_in>="000000000010011100010000" then mid_in<=mid_in-"000000000010011100010000";
d4<=d4+1;
present_state<=s1;
elsif mid_in>="000000000000001111101000" then mid_in<=mid_in-"000000000000001111101000";
d3<=d3+1;
present_state<=s1;
elsif mid_in>="000000000000000001100100" then mid_in<=mid_in-"000000000000000001100100";
d2<=d2+1;
present_state<=s1;
elsif mid_in>="000000000000000000001010" then mid_in<=mid_in-"000000000000000000001010";
d1<=d1+1;
present_state<=s1;
elsif mid_in>="000000000000000000000001" then
mid_in<=mid_in-"000000000000000000000001";

d0<=d0+1;
present_state<=s1;

else
present_state<=s2;
end if;

when s2=>

y0<=d0;y1<=d1;y2<=d2;y3<=d3;y4<=d4;y5<=d5;y6<=d6;y7<=d7;

present_state<=s0;
when others=>
present_state<=s0;
end case;
end if;
end process;
end behav;