FPGA静态显示8位7段数码的一个或多个的VHDL程序

library ieee;
use ieee.std_logic_1164.all;

entity segbcd is
port(
bcdin:in std_logic_vector(3 downto 0);
segout:out std_logic_vector(7 downto 0));
end entity segbcd;

architecture test of segbcd is
begin
with bcdin select
segout <= "11000000" when x"0",
"11100111" when x"1",
"11101101" when x"2",
"10000011" when x"3",
"10100101" when x"4",
"10001001" when x"5",
"10001000" when x"6",
"11100011" when x"7",
"10000000" when x"8",
"10000001" when x"9",
"--------" when others;
end test;