EDA2位二进制全加器的设计程序（用VHDL语言） 求解

有几种方法，下面给你个简单直接的
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder2b is
port(cin；ins td_logic;
a,b: in std_logic_vector(2 downto 0);
s: out std_logic_vector(2 downto 0);
cout: out std_logic);
end adder2b;
architecture vhd of adder2b is
signed sint:std_logic_vector(3 downto 0);
signed al,bl:std_logic_vector(3 downto 0);
begin
al<='0'&a;
bl<='0'&b;
sint<=al+bl+cin;
s<=sint(2 downto 0);
cout<=sint(3);
end vhd;