FPGA verilog实现键控数码管动态显示 急啊！！

module Display(

  D0,

  D1,

  D2,

  D3,

  Q,

  COM,

  Enable,

  clk

 );

input [3:0] D0,D1,D2,D3;

input Enable,clk;

output [7:0] Q;

output [3:0] COM;

reg [3:0] COM;

reg [7:0] Q;

reg [3:0] Dn;

reg [1:0] state;

always@(posedge clk)

begin

state <= state + 2'b1;

end

always@(posedge clk)

begin

if(!Enable) begin COM <= 4'b1111; Dn <= 4'b1111; end

else

begin 

case(state)

2'b00: begin Dn <= D0; COM <= 4'b1110; end

2'b01: begin Dn <= D1; COM <= 4'b1101; end

2'b10: begin Dn <= D2; COM <= 4'b1011; end

2'b11: begin Dn <= D3; COM <= 4'b0111; end

endcase

end

end

always@(Dn)

begin

case(Dn)

4'd0: Q = 8'b0000_0000;

4'd1: Q = 8'b0000_0001;

4'd2: Q = 8'b0000_0010;

4'd3: Q = 8'b0000_0011;

4'd4: Q = 8'b0000_0100;

4'd5: Q = 8'b0000_0101;

4'd6: Q = 8'b0000_0110;

4'd7: Q = 8'b0000_0111;

4'd8: Q = 8'b0000_1000;

4'd9: Q = 8'b0000_1001;

default: Q = 8'b0;

endcase

end

endmodule

做一个2位计数器，用来扫描4个数码管就行了，用case语句