MATLAB3线8线的译码器的设计

楼主可以参考：
http://hi.baidu.com/hongjingfen/blog/item/d67d31ee079df9f8b3fb95bb.html
3线-8线译码器设计
1.
按照以上介绍的ModelSim软件的一般使用方法，编写Verilog源程序，设计3线-8线译码器(门级描述);
module
decode38(s1,s2,s3,a0,a1,a2,y0bar,y1bar,y2bar,y3bar,y4bar,y5bar,y6bar,
y7bar);
input
s1,s2,s3;
input
a0,a1,a2;
output
y0bar,y1bar,y2bar,y3bar,y4bar,y5bar,y6bar,y7bar;
wire
s1bar,s2bar,s3bar;
//声明中间变量
wire
a0bar,a1bar,a2bar;
wire
gs;
not(s1bar,s1);//非门引用
not(s2bar,s2);
not(s3bar,s3);
not(a0bar,a0);
not(a1bar,a1);
not(a2bar,a2);
and(gs,s1,s2bar,s3bar);//与门
nand
g0(y0bar,a0bar,a1bar,a2bar,gs);
//与非门
nand
g1(y1bar,a0bar,a1bar,a2bar,gs);
nand
g2(y2bar,a0bar,a1,a2bar,gs);
nand
g3(y3bar,a0,a1,a2bar,gs);
nand
g4(y4bar,a0bar,a1bar,a2,gs);
nand
g5(y5bar,a0,a1bar,a2,gs);
nand
g6(y6bar,a0bar,a1,a2,gs);
nand
g7(y7bar,a0,a1,a2,gs);
endmodule