library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity lsd is
port(clk:in bit;
led:out bit_vector(7 downto 0));--位矢量和led_t一致
end lsd;
architecture led1 of lsd is
signal led_t:bit_vector(7 downto 0):="11111110";--信号初始化直接在这面
begin
process(clk)
begin
if (clk'event and clk='1') then
led_t<=led_t rol (1) ;
end if;
led<=led_t;
end process;
end led1;
楼上应该是对的
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