module counter16(out,count,data,load,cin,clk);
output [15:0] out;
output count;
input [15:0]data;
input load,cin,clk;
reg [15:0] out;
always@(posedge clk)
begin
if(load)
out = data;
else
out = out+cin;
end
assign count=&out&cin;
endmodule