用verilog HDL实现数字钟整点报时，几点就响几下

`timescale 1s/0.1s
module clock(reset);
input reset;
output [5:0] hour,min,sec;
reg[5:0] hour,min,sec;
initial begin
clk=1'搏谨b0;
forever #0.5 clk=~clk;
end

always@(posedge clk or reset)
if(reset)
begin
hour<=6'b0000_0;
min<=6'b0000_0;
sec<凳圆=6'b0000_0;
end
elseif(sec!=6'b111011)
begin
sec<=sec+6'b0000_1;
end
elseif(sec==6'b111011)
begin
if( min!=6'b111011)
begin
sec<=6'b0000_0;
min<=min+6'b0000_1;
end
elseif(min==6'b111011)
begin
if(hour!=6'b011000)
begin
hour<=hour+6'b0000_1;
sec<=6'枣银塌b0000_0;
min<=6'b0000_0;
end
elseif(hour==6'b011000)
begin
hour<=6'b0000_0;
sec<=6'b0000_0;
min<=6'b0000_0;
end
end

always@(hour)
repeat(hour) #1 beats ;

task beats;
//define beats event;
endtask

endmodule
beats事件为响铃操作任务。