三输入与非门VHDL源程序。

2025-03-10 17:19:22
推荐回答(2个)
回答1:

ENTITY nand3 IS
PORT (in1,in2,in3: IN bit; y: OUT bit);
END nand3;
ARCHITECTURE rtl OF nand3 IS
BEGIN
y <= NOT (in1 AND in2 AND in3);
END rtl;

回答2:

if ( in1=='1' and in2 =='1' and in3=='1') then
out1 = '0';
else
out1 ='1'
end if;