LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY yimaqi IS
PORT (ain:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dout:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END yimaqi;
ARCHITECTURE one OF yimaqi IS
BEGIN
PROCESS(ain)
BEGIN
CASE ain IS
WHEN "0000"=>dout<="0111111";
WHEN "0001"=>dout<="0000110";
WHEN "0010"=>dout<="1011011";
WHEN "0011"=>dout<="1001111";
WHEN "0100"=>dout<="1100110";
WHEN "0101"=>dout<="1101101";
WHEN "0110"=>dout<="1111101";
WHEN "0111"=>dout<="0000111";
WHEN "1000"=>dout<="1111111";
WHEN "1001"=>dout<="1101111";
WHEN "1010"=>dout<="0111001";
WHEN "1011"=>dout<="1011110";
WHEN "1100"=>dout<="1011100";
WHEN "1101"=>dout<="1010100";
when "1110"=>dout<="1111011";
WHEN OTHERS=>dout<="0000000";
END CASE;
END PROCESS; END one;
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