verilog 状态机

always@(posedge clk)
if(rst) begin
state<= 0;
clk<= 0; end
else begin
case(state)
0:begin
if(k1==1'b1) begin
clk<= tc2;
state<= 1; end
else begin
clk<= tc1;

state<= 0; end

end
1: begin
if(k1==1'b1) begin
clk<= tc3;
state<= 2; end
end
2: begin
if(k2==1'b1) begin
clk<= tc2;
state<= 3; end
end
3: begin
if(k2==1'b1) begin
clk<= tc1;
state<= 0; end
end

endcase end