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module gj;

// Inputs
reg clk;
reg [7:0] sw;

// Outputs
wire hsync;
wire vsync;
wire [2:0] red;
wire [2:0] green;
wire [1:0] blue;

// Instantiate the Unit Under Test (UUT)
vga5 uut (
.clk(clk),
.sw(sw),
.hsync(hsync),
.vsync(vsync),
.red(red),
.green(green),
.blue(blue)
);

initial begin
// Initialize Inputs
clk = 0;
sw = 0;

// Wait 100 ns for global reset to finish
#100;
sw=1;
reg [15:0] i;
for(i=0;i<=1000000;i=i+1)
begin
#1;
clk=~clk;
end
// Add stimulus here

end

endmodule
ERROR:HDLCompiler:806 - "E:/ise/vga1/vga5/gj.v" Line 57: Syntax error near "[".
ERROR:HDLCompiler:69 - "E:/ise/vga1/vga5/gj.v" Line 58: is not declared.
ERROR:HDLCompiler:598 - "E:/ise/vga1/vga5/gj.v" Line 25: Module ignored due to previous errors.